| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 100 === In the analog integrated circuit design process, researchers have proposed the concept of parameterized layouts in order to mitigate the problem of redesign iterations. Additionally, in order to use corner stitching data structure in storing parameterized layouts, polygons in parameterized layouts have to be partitioned. In the thesis, a parallel polygon partitioning algorithm, which is capable of partitioning parameterized 45-degree polygons into trapezoids and is based on the dual-scanline technology, is proposed. This technology uses two scanlines, which include top-down and bottom-up scanlines, so that vertices of a polygon can be concurrently processed. The algorithm can be used to deal with not only parameterized polygons, but also fixed-coordinate polygons. In addition, the performance of a procedure in the algorithm has been improved. Compared with a partitioning program implemented previously, the new parallel partitioning program can achieve as high as 2.34X speedup while using four threads.
|
|---|
