| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 100 === Reducing test application time and test data volume are major challenges in SoC design. In this thesis we propose a new dictionary-based test data encoding technique for multi-scan-based designs. To reduce the data volume transferred from ATE to the core under test, we classify the data segments of the scan chain into four groups. Four different lengths of indices are then assigned for all classes of segments to point to the entries of the dictionary. When sending a high using frequency of segments, only low portion of address is needed and the data volume can then be reduced. The decompression logic in the core under test is very simply and we can get high compression ratio by using variable encoding technique without increasing the complexity of decompression logic. Compare with other papers, this paper can improve the compression rate over 17%, through the big of the circuits, the effect will significantly obvious.
Dictionary-based is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test and it is especially suitable for a reduced pin-count and low-cost DFT test environment. Experimental results show the proposed approach indeed can get a high compression ratio of the test data and can as well reduce the test times.
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