| Summary: | 碩士 === 國防大學理工學院 === 機械工程碩士班 === 101 === As the trend of the semiconductor components was developed toward smaller and lighter, the thermal and thermo-stress problems on microelectronic packaging increase at the same time. Consequently, stresses are generated between the material in a packaging structure due to the differences on temperature distributions and the thermal expansion coefficient during manufacturing, testing and operation, and the problems need to be overcome for the packaging products.
This thesis uses the commercial ANSYS 13.0 finite element software to analyse the thermal and thermo-stress characteristics on high power diode packaging inside a typical power adapter. To this end, the equivalent equations to simplify the PCB(printed circuit board) material were first employed since the PCB structure is very complex. The global simulation were next performed with boundary conditions derived from iterations and verified through the comparisons with temperature measurements, and the temperature and displacement results on the PCB were then retrieved as the boundary conditions for the followed local simulations. Finally, The local models were built for both traditional diode packaging and the newly developed packaging with structure details, and thermal resistances and thermo-stresses on the models were next simulated. The results in this study shows that the newly designed packaging has better thermal resistance and smaller chip stresses than the traditional ones. Therefore, better reliability on the new packaging was verified through this work.
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