A 0.5V/1.0V Low-Power Delay-Recycled All-Digital Duty-Cycle Corrector with Unbalanced Process Variations Tolerance
碩士 === 國立中正大學 === 資訊工程研究所 === 101 === Due to the unbalanced rise time and fall time of the clock tree buffers, the duty-cycle of the on-chip clock may be distorted when it is distributed through the clock buffers to every module. However, for high speed data communication applications, such as doubl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37616770641066423586 |