| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 101 === Due to the unbalanced rise time and fall time of the clock tree buffers, the duty-cycle of the on-chip clock may be distorted when it is distributed through the clock buffers to every module. However, for high speed data communication applications, such as double data rate synchronous dynamic random access memory (DDR SDRAM) and double sampling analog-to-digital converter (ADC), it requires to sample the input data via the positive and negative edges of the reference clock. Duty-cycle error causes malfunction in these applications. For the sake of this requirement, a duty-cycle corrector (DCC) is employed in the system-on-a-chip (SoC) to correct the distorted clock.
With the growing recognition of energy savings, designing low-power electronic devices is demanded. According to the dynamic power dissipation equation, P=C(V^2)f, if we reduce the supply voltage to one-half of the nominal voltage, it can reduce 75% of power dissipations. However, the operating voltage near to the threshold voltage makes transistors charging and discharging slower. Hence, the intrinsic delay of logic gates becomes longer and directly affects the overall chip performance.
Hence, an all-digital duty-cycle corrector (ADDCC) with dual supply voltage mode and unbalanced process variation tolerance is presented in this thesis. The proposed ADDCC is implemented in TSMC 90nm CMOS process with standard cells. The proposed ADDCC has following characteristics: fast lock-in time, low area cost, low power consumption and high precision in duty-cycle correcting. Therefore, it is very suitable for low-power applications.
Index Terms — All-Digital Duty-Cycle Corrector, Delay-Recycled Half-Cycle Delay Line, Time-to-Digital Converter, Unbalanced Process Variations Tolerance.
|
|---|
