Multi-Bit Successive Approximation ADC with a Reduced Input Capacitor Using a Ring Counter Controller
碩士 === 國立中正大學 === 電機工程研究所 === 101 === A Multi-bit successive approximation analog-to-digital converter (SA ADC) with a reduced input capacitor using a ring counter controller is presented. The converter is implemented by the TSMC 90 nm CMOS process. At 50MS/s and 10 bit resolution, the ADC achieves...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23845216463163797736 |