| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 101 === A Multi-bit successive approximation analog-to-digital converter (SA ADC) with a reduced input capacitor using a ring counter controller is presented. The converter is implemented by the TSMC 90 nm CMOS process. At 50MS/s and 10 bit resolution, the ADC achieves an SNDR of 60.24 dB and consumes 1.404mW, resulting in a figure of merit (FOM) of 33.4 fJ/conversion-step. Compared to the conventional Multi-Bit SA ADC , the input capacitance is reduced about 66%. Reducing the loading effect for the former circuit. Due to using the ring counter, control circuit is simplified. On the other hand significantly reducing the dynamic power consumption. Compared to the conventional Multi-bit SA ADC, the average switching energy and dynamic power consumption of SAR Logic are reduced by about 29% and 72%.
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