Implementation of High Quality Timing Phase Locked Loop Based on FPGA
碩士 === 中華科技大學 === 電子工程研究所碩士班 === 101 === The paper relates to design, simulation and implementation of All Digital Phase Locked Loop (ADPLL) in Field Programmable Gate Array (FPGA). Besides quality improvement for phase locked loop (PLL), accuracy improvement for phase lock and flexible programmi...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/08884596267061243518 |