The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs

碩士 === 中原大學 === 電子工程研究所 === 101 === In modern VLSI designs, the minimization of power consumption is a very important issue. To minimize power consumption, the use of multiple voltages is a useful approach. However, in a multi-voltage design, the clock skew control becomes very complicated. Previous...

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Main Authors:	Yao-Chung Cheng, 鄭曜鐘
Other Authors:	Shih-Hsu Huang
Format:	Others
Language:	zh-TW
Published:	2013
Online Access:	http://ndltd.ncl.edu.tw/handle/3kb3k6

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spelling	ndltd-TW-101CYCU54280552019-05-15T21:02:51Z http://ndltd.ncl.edu.tw/handle/3kb3k6 The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs 多重電壓時鐘樹之延遲補償最小化 Yao-Chung Cheng 鄭曜鐘碩士中原大學電子工程研究所 101 In modern VLSI designs, the minimization of power consumption is a very important issue. To minimize power consumption, the use of multiple voltages is a useful approach. However, in a multi-voltage design, the clock skew control becomes very complicated. Previous works use the delay compensation method to achieve always zero skew among different voltage modes. As a result, a large amount of compensated delay is often required. Based on that observation, in this paper, we try to utilize useful skew among blocks to reduce the amount of compensated delay. We propose a linear programming (LP) approach to formally draw up this problem. Compared with the previous work, experimental results show that our approach can reduce 19.08% compensated delay. Shih-Hsu Huang 黃世旭 2013 學位論文 ; thesis 44 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中原大學 === 電子工程研究所 === 101 === In modern VLSI designs, the minimization of power consumption is a very important issue. To minimize power consumption, the use of multiple voltages is a useful approach. However, in a multi-voltage design, the clock skew control becomes very complicated. Previous works use the delay compensation method to achieve always zero skew among different voltage modes. As a result, a large amount of compensated delay is often required. Based on that observation, in this paper, we try to utilize useful skew among blocks to reduce the amount of compensated delay. We propose a linear programming (LP) approach to formally draw up this problem. Compared with the previous work, experimental results show that our approach can reduce 19.08% compensated delay.
author2	Shih-Hsu Huang
author_facet	Shih-Hsu Huang Yao-Chung Cheng 鄭曜鐘
author	Yao-Chung Cheng 鄭曜鐘
spellingShingle	Yao-Chung Cheng 鄭曜鐘 The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
author_sort	Yao-Chung Cheng
title	The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
title_short	The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
title_full	The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
title_fullStr	The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
title_full_unstemmed	The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
title_sort	minimization of compensated delay for multi-voltage clock tree designs
publishDate	2013
url	http://ndltd.ncl.edu.tw/handle/3kb3k6
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The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs

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