Analysis and Compensation for the Overlay Modeling Errors in Lithography Process of Wafer Stepper
碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 101 === In the lithography process of a very large-scale integrated circuits device, the micro-lithography is a critical step. The accuracy of overlay is one of the key factors for the yield of the integrated circuit (IC) manufacturing. In order to increase the resolut...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/07690428290902481809 |