Design and Implementation of Phase-Locked Loop With Cyclic Clock Generator to Enhance Loop-Bandwidth
碩士 === 華梵大學 === 電子工程學系碩士班 === 101 === Abstract Phase-Locked Loops(PLL) are widly used of Wired and wireless transmission , with the progress of the Semiconductor , the evolution of the circuit area is getting smaller and smaller , and each of area needs to be effectively utilized . The most of area...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78515123925727644903 |