Design of 10 Gb/s CMOS Limiting Amplifiers
碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 101 === In this thesis, we design a limiting amplifier with interleaving active feedback and a limiting amplifier with multiple active feedback. The two chips are implemented in the TSMC 0.18μm CMOS technology. Our circuits are designed with differential inputs...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22346900643000226930 |