Design of 10 Gb/s CMOS Limiting Amplifiers

• Main Authors: Feng-Zhu Wu, 吳豐竹
• Other Authors: Jau-Ji Jou
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/22346900643000226930

碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 101 === In this thesis, we design a limiting amplifier with interleaving active feedback and a limiting amplifier with multiple active feedback. The two chips are implemented in the TSMC 0.18μm CMOS technology. Our circuits are designed with differential inputs and differential outputs. The first limiting amplifier with interleaving active feedback includes the DC offset cancellation circuit, an output buffer with a transition frequency doubler, and an active inductors at the output ends. The voltage gain of this chip is 39 dB, its bandwidth is 10 GHz, its power consumption is 211.3 mW, and its output voltage swing is 520 mVpp. The second limiting amplifier with multiple active feedback includes a same DC offset cancellation circuit, and a same output buffer, and a negative capacitance circuit at the output ends. This chip has 43.1 dB voltage gain, 8.8 GHz bandwidth, 212.8 mW power consumption, and 550 mVpp output voltage swing. In this thesis, our limiting amplifiers can be applied to the optical receivers of SONET OC-192 or 10GEPON systems.