| Summary: | 碩士 === 明新科技大學 === 電子工程研究所 === 101 === With the advancement of technology, the feature size of field-effect transistors coming from semiconductor manufacturing technology has evolved from sub-micron to 28nm process generation or beyond. Following the Moore's law, besides the reduction of process cost and the increase of device density in ICs due to the dimensional shrinkage of transistor devices, the increase of transistor switch speed is chiefly considered. Recently, many researchers proposed several strain engineering processes to promote the electrical characteristics of devices. In strain technology, there are two species: tensile strain and compressive strain. In the view of structural design, there are bi-axial strain (or global strain) and uni-axial strain (or local strain), causing tensile or compressive effect on device channel to improve the channel mobility. Because of these strain techniques, the effective mass or the probability of scattering for channel carriers will be reduced and the channel mobility will be relatively enhanced.
In addition, to continuously scale down the feature size of CMOS devices, the gate leakage due to direct tunneling effect is huge to degrade the IC performance if the gate dielectric is still silicon dioxide, especially at 45 nm process or beyond. At that time, the thickness of gate dielectric is around 13Å or below. The short channel effect will be more obvious and the physical limitation will be quickly approached. Through the incorporation of high-k and metal gate process technology has a chance to suppress these drawbacks due to device shrinkage.
However, there usually exists some bad bonding quality between high-k material and silicon channel surface. Forming a thin layer of interfacial layer as a buffer layer is a possible way to solve this interface issue, but may not be perfectly achieved. In this work, we focus on the S/D junction integrity with HK/MG process and the punch-through effect with the combination of strain technology or channel size variation. Furthermore, some strained devices under 45nm process will be treated as a control group to probe the shift among these devices under test.
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