Cost-Effective Hardware Sharing Architecture Design of Fast 4x4 and 8x8 Integer Transforms for Multi-Standard Video Codecs
碩士 === 國立中興大學 === 電機工程學系所 === 101 === In this thesis, the research destination is to reduce the chip area by using hardware sharing techniques to multiple 4x4 and 8x8 integer discrete cosine transforms for multiple video coding standards. The proposed hardware sharing architecture supports two sizes...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/vm5k4d |