Studies of Novel Processing Technologies for Nano CMOS Device Applications

• Main Authors: Hung-YuChiu, 邱宏裕
• Other Authors: YK Fang
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/79175923032847322963

博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 101 === This dissertation presents various skills; including a new STI (shallow trench isolation) etch method, small grain size with low temperature polygen process, post-nitridation annealing (PNA) and the carbon co-implant to promote nano CMOS device performances. First, we use automatically top corner rounding (ATCR) STI etch to improve CMOS narrow width device performances. Compared to the conventional methods, the ATCR could increase 8% of the driving current (Idsat) together in a unit process step, thus getting easy process control and cost down benefits. Additionally, the ATCR has a wider process window. Besides, the technique does not degrade the gate oxide integrity, and junction leakage current. Next, we reduce the grain size of poly Si gate by lowering deposition temperature to achieve low sub-threshold leakage and gate leakage. This is due to the smaller grain size can offer a smoother interface to an ultra-thin gate oxide than a big one. Besides, the driving currents are also respectively increased ~9% and ~7% for n- and p- MOSFETs, as the temperatures are lowered from 715oC to 705oC. The most importance is that the small grain size does not degrade the gate oxide integrity and device junction leakage current. Additionally, used a high temperature post-nitridation annealing (PNA) to improve nano devices with pulsed radio frequency decoupled plasma nitrided ultra-thin (〈 50Å) gate dielectric. Results indicate that for a n-type MOSFET, as the PNA temperature rising from 1000oC to 1050oC, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. In final, a new molecular carbon co-implant technique was developed. The introduction of carbon ions induces the tensile strain to enhance the mobility. We optimized the dose and energy ranges for both P and C implants along with some anneal parameters to produce low sheet resistance (Rs) and high tensile strain. Besides, Rs measurement, SIMS, XTEM and HRXRD techniques were employed to characterize the doped layer. The optimized implants effectively improved 55nm n-MOSFET performances with Idsat 4.7% gain and significantly reduced transient enhanced diffusion (TED) due to the formation of SiC complex to sink Si interstitials.