| Summary: | 博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 101 === Recent years, NAND flash storage drive is one of the most important products used in smart mobile phone. The NAND Flash device is with the advantages which are high scalability and fast storage speed. The main purpose of this thesis is about the reliability studies of NAND Flash Cell and Periphery. Since the NAND flash needs high voltage around 20V during program / erase operation and median-low voltage around 10V during read operation, respectively, the periphery devices have to provide various kinds of voltages for NAND Flash operation. The first part research in this thesis focused on the studies of off-state breakdown and reliability of High-Voltage LDMOS Transistors. Finally, the reliability of NAND Flash Cell will be discussed in the final section.
The high voltage which is applied to NAND Flash Cell for Program/Erase operation is through 2 stages circuits. The first stage circuit is level-shift circuit and then word-line driver circuits. In level-shift circuit, one of the used devices is depletion-mode high-voltage LDMOS. For application, the high off-state breakdown (off-state BD) is one of the requirements for this device in level-shift circuit. In the experiments, we found that the off-state breakdown is dominated by gate-induced-drain-leakage (GIDL) and junction breakdown (BDj). The off-state BD increased with higher dosage of LDMOS N- drift region first and decreased finally, likes Bell-shape curve with an optimized point. The major mechanism of optimized point is caused by the uniform electric field (E-field) distribution. As the dosage of LDMOS N- drift region is with too heavy or slight may induce the E-field to close to gate edge or n+ portion, caused the off-state BD drop. Besides, in this work, we also based on the realized mechanism to find a method which is deeper implant make more margin for process variation.
The second stage is the word-line driver circuit which used enhanced-mode LDMOS. In this thesis, we proposed using gradual screen oxide replace uniform ones before the implant N- drift region of LDMOS. Thus, the implant process faces gradual screen oxide and induced gradual junction profile for N- drift region of LDMOS. The gradual junction profile effectively reduces the E-field for not only on-state but also off-state operation. The improvements include 2nd stage ISUB by Kirk Effect, off-state BD, hot carrier reliability and electrical safe-operating-area (E-SOA).
In the final section of this thesis, the extraction of interface state (Nit) had discussed for a NAND Flash Cell device. We successfully extracted and separated the Nit in corner region and center region of device in width direction, respectively. Since NAND Flash is with the structure of recess control gate, the charge pumping current (ICP) will be impacted by the data states like program and erase states. Because of the program and erase state are with positive and negative VTH/VFB, respectively. From the TCAD result, as the cell is erased, the density of electron inversion layer will be reduced by control gate with negative voltage. The ICP is contributed from center area and reflects the center Nit. On the other hand, control gate is biased positive voltage to monitor ICP in program state. Although the control gate with positive voltage causes higher electron density in the corner region, the thermal emission occurring neglects the impact to ICP. In program state, the charge pumping reflects the Nit of whole region. Besides, three level charge pumping method is used to monitor the Nit with energy distribution and support the extraction of Nit in center and corner region. Finally, the reliability of NAND Flash is discussed. Based on previous extraction results, experiment results show that the corner Nit is with worse degradation than center Nit due to higher corner E-field. The degradation extends from corner to center during stressing.
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