Interface morphologies and electrical properties of bonded Ge/Si wafers

• Main Authors: Chiu, Yu-Chia, 邱郁珈
• Other Authors: Wu, Yew-Chung
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/06230961287785022027

碩士 === 國立交通大學 === 材料科學與工程學系所 === 101 === Silicon and Germanium integrated for applications in optical communication systems and interconnection have attracted much attention. The formation of a heterojunction between hybrid materials by wafer bonding technique has been generally successful. During high pressure and high temperature annealing process, wafers are bonded by producing covalent bonds at interface. However, the high temperature annealing produced cracks in both wafers caused by large difference in the thermal expansion coefficients of Ge and Si, resulting in low yield for device fabrication. In this study, direct wafer bonding technique was applied to combine p-type Ge/Si and n-type Ge/Si. First, mesa structures fabricated on silicon wafers were used to avoid thermal stress during high temperature annealing process. The interface microstructure was investigated by transmission electrical microscopy (TEM) and I-V characteristic was also measured. The thickness of amorphous decreased with the annealing temperature increasing. The result of the I-V measurement also showed that the breakdown and the turn-on voltage decreased with the annealing temperature increasing, because the thickness of amorphous at interface changed with temperature. Results of I-V measurements and energy band diagram found that high temperature annealing did not meet the trend of the energy band alignment diagram, presumably due to germanium atoms and silicon atoms diffused between interfaces and caused the trap-assisted tunneling effect, the carriers could cross the barrier at interface.