Performance, Manufacturability, and Yield Optimization in Nanometer Design Routing
博士 === 國立交通大學 === 資訊科學與工程研究所 === 101 === As very-large-scale integration (VLSI) designs enter the nano-meter area, many methodologies are introduced to shorten the time-to-market or improve the manufacturability of chips; however, the introduced methodologies bring new issues into the design flow. I...
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96693157871309692858 |