| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === This thesis investigates the feasibility of threshold voltage (Vth) modulation through substrate bias for tri-gate MOSFETs. Through 3-D atomistic simulation, the random dopant fluctuations in the Punch-Through-Stopper (PTS) region of Bulk tri-gate devices are examined. Our study indicates that to achieve an efficient threshold-voltage modulation through substrate bias, the high-doping PTS region may introduce excess variation in Bulk tri-gate devices. This effect has to be considered when one-to-one comparisons between Bulk tri-gate and SOI tri-gate regarding device variability are made.
Because of the PTS-induced variability in Bulk tri-gate, SOI tri-gate with substrate bias seems to be a better device structure to achieve multiple Vth. In order to facilitate multi-Vth device design in tri-gate SOI MOSFETs, we have derived an analytical subthreshold model with an accurate BOX-thickness scalability. Using this model, we can efficiently investigate multi-Vth device design in tri-gate SOI MOSFETs with wide range of design space. Under constant subthreshold swing criterion, our study indicates that tri-gate SOI device with low aspect ratio (AR) and thin BOX is a promising structure to enable efficient Vth modulation by substrate bias.
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