| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === In this thesis, we have successfully fabricated n-type juntionless (J-less) independent double-gated (IDG) poly-Si nanowire (NW) transistors which have highly doped channels but can be effectively turned off on account of the ultra-thin feature size of NWs. In addition, the electrical characteristics are well compared to the conventional devices with undoped channels which operate in the inversion mode (IM).
Owing to the fact that the current conduction is through the whole Si channel, the Ion characteristics are obviously better for the J-less devices, so do the output characteristics. Moreover, due to the flexibility in device operation offered by the two independent gates, the differences of conduction mechanisms between the two types of devices can be clarified and confirmed by the TCAD simulation results. We also found that short channel effects (SCEs) are more severe for the J-less devices, which is ascribed to the additional equivalent oxide thickness (EOT) contributed by the surface depletion layer. Also, the J-less devices have poorer gate controllability under the SG mode owing to the thicker EOT, resulting in the more negative Vth over that of the DG mode. On the other hand, the higher channel doping concentration the J-less devices have, the harder the J-less devices can be effectively turned off at Vg = 0. Moreover, as the channel doping concentration is higher, the SCE for the J-less devices gets much worse, and the Vth of the device becomes more sensitive to the channel doping. Also, utilizing the TCAD simulation, we can extrapolate that the J-less devices with lower channel doping concentration possess better gate controllability since they can more effectively modulate the depletion region with varying gate overdrive. Finally, as the channel doping is sufficiently high, the J-less devices show Vth characteristics (DG > SG-2 >SG-1) opposite to those observed for the IM devices.
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