A Circuit-Topology-Guided Discrete Gate Sizing Framework Considering Leakage Power Reduction
碩士 === 國立交通大學 === 電子研究所 === 101 === Gate sizing is a classic problem in the field of electronic design automation (EDA), and has been extensively studied for several decades. However, in the modern era, it is desired to have designs with both high performance and low power consumption. When dealing...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64986749298884156305 |