Accelerometer Design with A Low-Power Capacitor to Frequency Readout Circuit
碩士 === 國立交通大學 === 電子研究所 === 101 === A monolithic accelerometer with integrated capacitance to frequency readout in mixed signal MEMS process is proposed. It directly converts to the frequency dependent signal by the integrator, the comparator and the digital logic circuit. Compared with capacitance...
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49861475790623103686 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === A monolithic accelerometer with integrated capacitance to frequency readout in mixed signal MEMS process is proposed. It directly converts to the frequency dependent signal by the integrator, the comparator and the digital logic circuit. Compared with capacitance to voltage readout circuit and analog to digital converter, the C to F converter can reduce the amount of hardware. The total area is 0.356mm*0.609mm without accelerometer. The readout circuit employs the switch capacitance charge integrator with chopper stabilization to suppress the flicker noise and offset. The integrator output rms noise is 636.6uV (integrating from 0 Hz~500 kHz) by Spectre RF simulation in UMC 0.18um technology. Due to the modified capacitance to frequency readout circuit structure, it can achieve the goal of low power and high resolution. The total power consumption and the circuit sensitivity are 225.77uW and 731.26 Hz/fF at 1.8V power supply by measurement result.
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