Area-Efficient BCH Codec with Fully Parallel Architecture for Latency-Constrained Memory Systems
碩士 === 國立交通大學 === 電子研究所 === 101 === Latency-constrained memories are utilized for the high throughput systems. As the memory process is scaling down, error control codes are used to improve reliability. In the thesis, a double error correcting (DEC) BCH codec is designed for latency-constrained memo...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/91532758779330390613 |