Performance of Vertical Gate-All-Around Si (110) and Si (551) MOSFET on Si(100) Substrate
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === Scaling beyond Moore’s Law has faced a big challenge due to the lithography limitation beyond the 10nm node. Several issues, such as device structures, channel materials, interface quality, capacitance and contact resistance, have been studied for beyond 14...
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46d89d |