Routability-Driven Bump Assignment for Chip-Package Co-Design
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually, the whole process costs a huge manual effort and multiple iterations thu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61838305486549089439 |