4ACE:A Double-layer Double-channel Array Capacitance Equilibrium Router
碩士 === 國立中央大學 === 電機工程學系 === 101 === As the shrink of semiconductor process, the process variation effects performance of circuit much more seriously. It also causes high complexity and time-consuming on designing circuits. Therefore, layout automation is likely to play a key role in analog circuit...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/07726353507992412941 |