2CWP-CABC: A Yield-aware Placement with Power-of-Two Cutting and Weighted Priority for the Capacitor Array Block Creator
碩士 === 國立中央大學 === 電機工程學系 === 101 === As the evolution of semiconductor process technology from 0.18um, 90nm to the present minimum is 22nm, the process variation will be more and more serious in device mismatch. This represents the analog circuit design increase time-consuming and high complex, then...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98107267057376134941 |