Area and Maximal Wire-length Optimization of Analog ICs Layout Generator
碩士 === 國立中央大學 === 電機工程學系 === 101 === Due to the sensitivity of analog components, and the size shrink of devices, post-layout electrical effects increasingly impact the circuit performance. In order to reduce the impact of electrical effects on circuits, the layout of analog circuits are mostly gene...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48459410818384424877 |