Design of Wide-Range Low-Power Delay- Locked Loops With Multi-Phase Outputs
碩士 === 國立東華大學 === 電機工程學系 === 101 === According to the advances in process technology, The development of VLSI systems is toward to system-on-a-chip(SoC). The system integration of each circuit module needs accurate clock signals to be synchronized. Delay-locked loops (DLLs) and Phase-locked loops (P...
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| Format: | Others |
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2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82102389804988528038 |