Heterogeneous QEMU-SystemC Integration for Timed CPU/Cache/MMU/DRAM/Component Simulation: A case study in 3D Graphics SoC
碩士 === 國立中山大學 === 資訊工程學系研究所 === 101 === Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace the original design flow. Today’s ESL can verify the whole system simulatio...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40199208130143064495 |