A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design

• Main Authors: Bang-Cyuan Chen, 陳邦權
• Other Authors: Ko-Chi Kuo
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/06564569866455010495

碩士 === 國立中山大學 === 資訊工程學系研究所 === 101 === A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is replaced by the energy efficient SAR ADC. By taking the advantages of the pipelined ADC with high speed and high resolution and the SAR ADC with low power consumption. 1. Using only two stages in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. Removing the front-end sample-and-hold circuit by capacitor array in the SAR ADCs and sample switch. Hence, the whole circuit only requires one operation amplifier which uses in MDAC circuit. 2. The comparators in the proposed ADC are dynamic comparators which consume no static power consumption. Capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve energy efficient and high speed applications. 3. An additional comparator for MSB is designed for the ADC using in sample phase. It can enhance the sample rate of ADC and relax the design difficulty of the operation amplifier in MDAC. 4. A capacitor array combined two kinds of capacitor array is proposed for pipelined-SAR ADC application.