High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter
碩士 === 國立中山大學 === 資訊工程學系研究所 === 101 === In this thesis, the circuits are designing with TSMC.18μm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100MS/s and 13-bits individually. The proposed pipelined stage replace the Flash ADC by the SAR ADC and add an extra comparat...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13291822431960433711 |