3D Variation-Aware Clock Tree Synthesis
碩士 === 國立清華大學 === 資訊工程學系 === 101 === The reliability of through-silicon via (TSV) is becoming increasingly important in 3D ICs. Since the higher failure rate of TSV in clock tree yields more bad chips. Accordingly, the previous work proposes a novel TSV fault-tolerant unit (TFU), which can provi...
Main Authors: | , |
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Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2013
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Online Access: | http://ndltd.ncl.edu.tw/handle/53564581982548678610 |