A Fully-Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

• Main Authors: Yang, Jeng-Da, 楊政達
• Other Authors: Ueng, Yeong-Luh
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/26617888119335096948

碩士 === 國立清華大學 === 電機工程學系 === 101 === In this thesis, we propose a Probabilistic Normalized Min-Sum Algorithm (PNMSA) for low-density parity-check (LDPC) decoders, where a probabilistic second minimum value is used in the check-node processing. Simulation results show that the proposed algorithm only introduces a minor performance degradation compared to the original normalized Min-Sum Algorithm. Based on the PNMSA, a fully-parallel decoder architecture is devised, where the check-node processing is implemented using several subunits and an efficient method is proposed to exchange messages between these subunits. With a carefully-chosen normalization factor, a satisfactory error-rate performance can be achieved using a lower number of quantization bits. In addition, look-up-table-based comparison with lower complexity is used to implement the check-node units. The proposed decoder was implemented using a 90-nm 1P9M CMOS process. Post-layout results show that the decoder occupies an area of 7.97 mm^2, achieves a throughput of 223.8-Gbps, and an energy efficiency of 14.9 pJ/bit.