Steep Subthreshold Slope Tunnel Field-Effect Transistor：Hetero-Tunneling, Orientation Effect and Ferroelectric Negative Capacitance Gate Stack
碩士 === 國立臺灣師範大學 === 光電科技研究所 === 101 === The happy scaling of classic FET has been finished, as strain engineering technology for 90 nm, and gate stack ( high-K + metal gate ) for 45 nm technology node. Intel claimed that the 3D structure of tri-gate is mainstream in 22nm technology node, this is an...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/dt3s2j |