A 1.47ps Low Jitter, 120MHz – 1.4GHz Wide-Range, and Fast-Locking All-Digital Delay-Locked Loop
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === In recent years, the trend of IC design goes toward to the system-level and single-chip solution. Therefore, we usually integrate many intellectual properties (IPs) and customized blocks into a single chip, named System-on-Chip (SoC). As a result, the DLLs ar...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85571250698167373520 |