Lithography Optimization for Sub-22 Nanometer Technologies

博士 === 國立臺灣大學 === 電子工程學研究所 === 101 === As integrated circuit (IC) process nodes continue to shrink to 22nm and below, the IC industry will face severe manufacturing challenges with conventional optical lithography technologies. According to the keynote speech at International Symposium on Physical D...

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Bibliographic Details
Main Authors: Shao-Yun Fang, 方劭云
Other Authors: 張耀文
Format: Others
Language:en_US
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/91452054312255317999
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Summary:博士 === 國立臺灣大學 === 電子工程學研究所 === 101 === As integrated circuit (IC) process nodes continue to shrink to 22nm and below, the IC industry will face severe manufacturing challenges with conventional optical lithography technologies. According to the keynote speech at International Symposium on Physical Design (ISPD) 2012 by Dr. Burn J. Lin from TSMC, three possible technologies may push the limits of lithography: multiple patterning lithography, electron beam lithography (EBL) and extreme ultraviolet lithography (EUVL). However, each of which encounters different design difficulties and requires solutions for a breakthrough. For overcoming the resolution limit of conventional optical lithography, multiple patterning lithography has been regarded as one of the most promising solutions. While litho-etch-litho-etch (LELE) double patterning lithography (DPL) has been widely used, self-aligned double patterning (SADP) has received more and more attention in recent years due to its better controllability of overlay and critical dimension (CD) uniformity. Two types of layout decomposition strategies are used to define two-dimensional layout patterns in SADP: positive and negative tones, in which spacers respectively define layout patterns with a cut mask and define spacings among patterns with a trim mask. Several algorithms have been proposed for negative tone layout decomposition. To the best of our knowledge, however, no algorithm has been proposed for positive tone layout decomposition, which could have the better decomposability for gridless designs. In this dissertation, we propose the first work of positive tone layout decomposition for SADP which can simultaneously minimize the conflicts on both the core mask and the cut mask. In addition to the conventional optical lithography, there are two most promising Next Generation Lithography (NGL) technologies: EBL and EUVL. Since EBL is not limited by light diffraction, the e-beam can define very fine, high resolution patterns in a resist. There are two critical issues in EBL: (1) the thermal problem and (2) the low throughput. For a single e-beam system for photomask fabrication, the e-beam writing process is usually performed in a contiguously sequential way, causing the high-voltage beam to deposit a considerable amount of heat in a small area and resulting in critical dimension (CD) distortion. To avoid the successive heating problem in EBL, we propose a graph-based subfield scheduling algorithm that reorders the sequence of the writing process with blocked box consideration. The other critical issue in the single e-beam system is the extremely low throughput due to the maskless direct write process. Recently, the concept of multiple e-beam lithography (MEBL) has been proposed, which utilizes massively parallel exposures with thousands or even millions of beams to dramatically improve the throughput. Due to the deflection limitation of each beam and parallel writing strategies in MEBL, a layout (a main field) is split into stripes (subfields), and we define the stripe boundaries as the stitching lines. A pattern cut by a stitching line suffers from overlay error between two beams or two writing passes, and the overlay error causes different impacts on different types of patterns. To reduce stitching line-induced bad patterns, we propose the first work of stitch-aware routing algorithms for generating MEBL-friendly designs. On the other hand, EUVL is the other probable NGL technology since the ten times reduction in wavelength used in EUVL offers the capability of a continuation of Moore''s law beyond the 22 nm technology node. However, due to the surface roughness of the optical system in EUVL, the rather high level of flare (i.e., scattered light) becomes one of the most critical issues. In addition, the layout density non-uniformity and the flare periphery effect (the flare distribution at the periphery is much different from that in the center of a chip) also induce a large flare variation within a layout. Both of the high flare level and the large flare variation could worsen the control of CD uniformity, and thus flare compensation strategies are required. In the dissertation, we also present the first work that solves the flare mitigation problem in EUVL with a specific dummiffication algorithm flow considering global flare distribution.