RTL Design Debugging Techniques for FSM-based Error Models
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === Given an erroneous RTL design and an error trace that demonstrates a mismatch between the specification and the design, automated design debugging techniques utilize this error trace and its simulation values on the circuit netlist to identify the potential err...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20668159463304140593 |