| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === Given an erroneous RTL design and an error trace that demonstrates a mismatch between the specification and the design, automated design debugging techniques utilize this error trace and its simulation values on the circuit netlist to identify the potential error locations in the RTL design. Notably, with the extreme high complexity of modern VLSI designs, it is virtually impossible to debug the designs without the help of automated algorithms. Therefore, automated design debugging plays a very important role in ensuring the successful design sign-off. However, in reality these automated debugging tools are not as popular as they should be. The main reason is because they are notorious for generating results with a huge number of error candidates. Consequently, designers have to spend a very long time to screen out the spurious error candidates manually. What is worse, as the error candidates are mostly annotated on the circuit netlist, it is also very time-consuming for the designers to figure out the actual causes of the error on the original RTL design by tracing the error locations in the circuit implementation. To conquer these problems, we propose an automated RTL debugging algorithm that works on the FSM-based error models. Instead of representing the error candidates in a circuit implementation, we classify the potential errors of a RTL design by considering different error scenarios on its corresponding finite-state machine model. These error candidates can then be directly mapped to error locations in the original RTL code. The experimental results show that our algorithm is able to effectively identify the actual errors among a small number of error candidates with our finite-state machine error model.
|
|---|
