Routability-Driven Blockage-Aware Macro Placement
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === To speed up the time to market for system-on-a-chip (SoC), a chip usually contains tens or even hundreds of intellectual property (IP) macros (e.g., analog blocks, embedded memories). Some of those macros, namely pre-placed macros, need to be placed at speci ed...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63160954198367982059 |