| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === To speed up the time to market for system-on-a-chip (SoC), a chip usually
contains tens or even hundreds of intellectual property (IP) macros (e.g., analog
blocks, embedded memories). Some of those macros, namely pre-placed macros,
need to be placed at speci ed locations for di erent issues, such as power, ther-
mal, and the connections with IO pads. In macro placement, the pre-placed macros
are treated as blockages and not allowed to overlap with other macros. Hence,
for complex designs with many pre-placed macros, it would incur the di culties of
nding a non-overlapping placement result. To handle the blockages and prevent
overlaps among macros, we propose a new circular-packing tree (CP-tree) oorplan
representation for our macro placement algorithm. A CP-tree could exibly pack
movable macros toward corners or toward pre-placed macros along chip boundaries
circularly to optimize the macro positions and preserve a complete placement re-
gion for standard-cell placement. Moreover, the macro positions and orientations
would signi cantly a ect the wirelength and routing congestion in the standard-cell
placement and routing stages, but most of existing macro placers only consider the interconnections among macros. Therefore, a routability-driven wirelength model
is presented to fast estimate the wirelength among macros and standard cells and
to consider the macro porosity e ect for better routability. Experimental results
show the e ectiveness and e ciency of our macro placement algorithm. Compared
with state-of-the-art academic macro placers, our algorithm obtains the best wire-
length results in ISPD 2006 placement benchmarks. Furthermore, for real industry
benchmarks, our algorithm can achieve the shortest routed wirelength results as
competitive as manual designs, compared with leading academic mixed-size placers.
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