Layout Optimization Using MTCMOS Technique for Low-Power SOC Applications
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis presents the method of using the MTCMOS technology to optimize the SOC chip considering layout via EDA tools. Chapter 1 presents the recent CMOS VLSI SOC design circuit trend. Then Chapter 2 describes MTCMOS technology and its applications. The appl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28018015933824509945 |