Low Power All-Digital Phase-Locked Loop with Open loop Mechanism for MEMS Oscillator
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis illustrates the design and implementation of low power all-digital phase-locked loop with open loop mechanism for MEMS oscillator. The digital phase-locked loop performs 72MHz output with hundreds ppm level frequency accuracy for a wide temperature...
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73820810792344310455 |