Low Power All-Digital Phase-Locked Loop with Open loop Mechanism for MEMS Oscillator

• Main Authors: Ci Li, 李琦
• Other Authors: 呂良鴻
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/73820810792344310455

碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis illustrates the design and implementation of low power all-digital phase-locked loop with open loop mechanism for MEMS oscillator. The digital phase-locked loop performs 72MHz output with hundreds ppm level frequency accuracy for a wide temperature range, which is designed to calibrate frequency drift of MEMS oscillator under temperature change. With open loop mechanism, we reduce 20% power consumption of digital phase-locked loop circuit, and estimated save 70% system power. By using a standard TSMC 65-nm and 0.18-μm CMOS process, there are three circuits implemented. Firstly, the digital frequency-locked loop architecture is introduced to accelerate the locking process. The proposed architecture is simply composed of digitally controlled oscillator, bang-bang phase detector, digital divider and binary gain shift logic circuit for reducing the hardware cost and power consumption. Secondly, the phase-injection mechanism is applied to phase-locked loop for continuous output. In order to reduce the power consumption, the proposed lock detector is present in the third digital phase-locked loop design. Operated at a 1-V supply voltage (1.2-V at 0.18-μm CMOS process), the fabricated circuits consume a dc power less than 1 mW. Except the testing circuits and pads, the active areas are all less than 1 mm2. The functions and performance are verified in the measurement result.