Realization of Multilevel-floorplanning on 3D-VLSI

• Main Authors: Je-Yan Su, 蘇哲彥
• Other Authors: Jyh-Perng Fang
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/wzrtsf

碩士 === 國立臺北科技大學 === 電機工程系研究所 === 101 === Technology is updated continuously. The number of the modules on the chip was complicated. It intends to influence the wirelength and make the design fail. Thus, the 2D planar architecture gradually moved into 3D stack architecture in recent years. Most of the existing floorplanner formulated each layer in the 3D stack into a flat plane and floorplan each layer independently. It would lose the information between layers, and let the relation modules be placed on different corners. Instead, we used an improved layer-aware multilevel floorplanning approach. It partitioned the modules into different layers by K-L algorithm, then used the same algorithm to perform uncorsening for the each layer. During uncorsening phase, modules of the same TSV’s matching will be put closely, even if they belongs to different layers. Then floorplan each partition is floorplanned independently. In our approach, corsening is not necessary. After floorplanning, we use an incremental scanning method to scan possible blank area to decide candidate TSVs, and then apply a TSV’s matching approach retain suitable TSVs from candidate TSVs. Experimental results show that multi-level floorplan with incremental scanning method and TSV’s matching can effectively speed up the calculation and shorten the wirelength.