12-bit/200MHz Digital Transmitter with Double Sampling-Rate for VDSL
碩士 === 國立臺北科技大學 === 電機工程系所 === 101 === This thesis describes the chip implementation of a 200MHz/double sampling-rate CMOS digital transmitter based on VDSL system specification. This digital transmitter is composed of a 12-bit, 200MHz digital-to-analog converter (DAC) operated in the proposed doubl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28ctf3 |