| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系所 === 101 === This thesis describes the chip implementation of a 200MHz/double sampling-rate CMOS digital transmitter based on VDSL system specification. This digital transmitter is composed of a 12-bit, 200MHz digital-to-analog converter (DAC) operated in the proposed double sampling-rate structure, and a fully differential current-mode line driver integrated with a 2nd-ordered transmitting filter. The digital transmitter had been fabricated with the TSMC 0.18μm 1P6M CMOS technology.
VDSL (Very High-Bit Rate Digital Subscriber Line) technology permits the transmission of asymmetric and symmetric data rate up to 100Mbps for upstream and downstream direction on twisted copper pairs using a signal bandwidth up to 30MHz. It can be deployed from fiber-optic connected cabinets located near the customer premises.
For such high-speed applications, the digital-to-analog converter adopts the switch-current mode architecture with a double sampling-rate operation. Under 200MHz clock frequency, the digital-to-analog converter can reach the equivalent 400MHz conversion rate. The simulation of 12-bit DAC shows that the maximum output current is 4095μA, and the conversion signal bandwidth is up to 30MHz.
To conform the bandwidth requirements of VDSL/VDLS2, a transmitting filter is used after the DAC stage to filter the high-frequency harmonics. With the DAC double sampling-rate operation mode, a 2nd-ordered filter is satisfactory in the bandwidth performance. The line drive circuit integrates a transmitting filter and a current-feedback amplifier with capacitor-feedforward compensation to reach high linearity and low harmonic distortion. According to the simulation result, the output voltage of the proposed line driver is 2Vpp at differential load of 100Ω.
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