| Summary: | 碩士 === 國立臺北科技大學 === 機電整合研究所 === 101 === Since 45nm process generation and beyond, high-k/metal-gate (HK/MG) combining strain engineering technology for nano-scale MOSFETs incorporated into the conventional CMOS process is available and promising to increase the drive current. In the past, after gate dielectric deposition, the annealing process with nitrogen gas was commonly adopted to repair the existence of defects in gate dielectric and therefore improve the quality of interfacial layer in MOSFETs. However, few published researches discussed the nitridation effect of decoupled plasma nitridation (DPN) process with the hot-carrier effect and electrical characteristics at different annealing temperatures. In this study, I focus on these points and try to establish these relationships.
In this work, the tested 28nm wafers came from UMC. The hafnium-based gate dielectric with a profile of HfOx/ZrOy/HfOz (HZH) was deposited with atomic layer deposition (ALD) technology. The experimental parameters include the different channel lengths and stress temperatures. Consequently, through the statistical and analytical analysis of experimental data, the nitridation effect with annealing temperatures reflecting the various results of device electrical characteristics are exposed in this thesis.
After the analysis, the annealing temperatures after DPN treatments do not obviously impact the device performance. Owing to the stronger horizontal electrical field, the degradation of short channel nMOSFETs with L=0.03?m in channel hot-carrier (CHC) stress is more serious than that with L=1?m. Additionally, for the identical L, the worst degradation of nMOSFETs with CHC test is the samples of 8% N2 concentration and 900℃ annealing temperature stressed at 125℃. This may attribute to the formation of thicker oxide interfacial layer (IL) and was annealed cause crystallization.
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