Chip Design of an Analog Low Power Sum-Product LDPC Decoder using Early Termination
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 101 === This thesis proposes an analog low power LDPC decoder employing new stopping iteration method. It is based on the sum-product algorithm and by checking parity H-matrix to decide iteration termination. The supply voltage of the proposed decoder only uses 1.2V...
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/dvtt8g |